The present invention relates to a semiconductor memory device for supplying a selection signal to a memory block to read out or write memory information from or in the memory block.
In recent years, various data are communicated via the Internet, and enormous amounts of data including image data and CAD information are transferred. Conventionally, in displaying such data while receiving them by a personal computer, they are temporarily stored in a hard disk and then subjected to necessary display processing because of a large amount of data. However, since the access time to a hard disk is long, necessary processing spends a long time. Recently, with the development of large-capacity semiconductor memory devices, a file memory device using a semiconductor memory device instead of the hard disk is proposed to shorten the processing time.
This file memory need not read out or write (to be referred to as read/write hereinafter) data from or in a memory cell at random, unlike a general semiconductor memory device. The file memory suffices to read/write data from/in memory cells in given successive areas. To achieve this purpose, some file memories can automatically access successive memory areas of a memory main body in a semiconductor memory device and successively read/write data while reducing the number of accesses from the CPU to the memory main body.
FIG. 10 shows the arrangement of a semiconductor memory device disclosed in Japanese Patent Laid-Open No. 7-296579.
In FIG. 10, reference numerals 101a to 101d denote memory cells storing data, which are connected to a word line WL for controlling output of data, and bit lines BL for outputting data. Reference numerals 102a to 102d denote sense amplifiers for amplifying the voltages of the bit lines BL. Data amplified by the sense amplifiers 102a to 102d are respectively input to column selectors 103a to 103d, the outputs of which are connected to an output circuit 104.
Reference numeral 108 denotes a control circuit for controlling a row decoder 105, the sense amplifier 102, and a precharge circuit 110; 109, an output control circuit for controlling the column selector 103; 106, a flag register storing a successive read flag representing the number of data to be successively read out; and 107, a cycle counter for referring to and counting up the value of the flag register in synchronism with clocks.
The operation of the semiconductor memory device shown in FIG. 10 will be explained with reference to timing charts shown in FIGS. 11A to 11F. The case wherein four memory cells are connected to one word line WL and data are successively read/written from/in three of them will be exemplified. FIG. 11A shows an output from a clock generating circuit (not shown).
In an initial state, i.e., the first half of a clock T51, the bit line BL is precharged to "1" by the precharge circuit 110 (FIG. 11C). In this state, the sense amplifiers 102a to 102d are kept inactive, and input/output data from the output circuit 104 is infinite (FIG. 11F).
When an access instruction is generated to successive memory areas of memory cells, a word line WL1 is activated at the trailing edge of the clock T51 in accordance with start address information (FIG. 11B). At this time, a read of successive 3-address data, i.e., "3" is written in the flag register 106 (FIG. 11D), and the cycle counter 107 is cleared to "0" (FIG. 11E).
After the word line WL1 is activated in the second half of the clock T51, memory data are read out onto respective bit lines BL from the memory cells 101a to 101d connected to the activated word line WL1 (FIG. 11C). At the same time, the sense amplifiers 102a to 102d are activated by a sense amplifier activation signal from the control circuit 108 to amplify the data on the bit lines BL and determine the contents of the memory cells on the respective bit lines.
In the second half of the clock T51, the memory cell 101a located at the intersection of the word line WL1 and a bit line BL1 is selected in accordance with start address information. The output of the sense amplifier 102a is connected to the output circuit 104 via the column selector 103a, and data of the memory cell 101a is output outside from the output circuit 104 (FIG. 11F).
With the next clock T52, the value of the cycle counter 107 is updated to "1". In accordance with the updated value and start address information, the column selector 103b is selected by the output control circuit 109. Then, the sense amplifier 102b is connected to the output circuit 104, and data corresponding to the memory cell 101b located at the intersection of the word line WL1 and column address "1" is output (FIG. 11F).
Subsequently, with a clock T53, the value of the cycle counter 107 is updated to "2". In accordance with the updated value and start address information, column address "2" is selected by the output control circuit 109. The sense amplifier 102c is connected to the output circuit 104, and data of the memory cell 101c is output (FIG. 11F).
When the value of the cycle counter 107 reaches "2", the value of the flag register 106 is cleared (FIGS. 11D and 11E). Thereafter, with a clock T54, the activation states of the word line WL1 and each sense amplifier are canceled by the control circuit 108, and the next memory access is prepared.
In this manner, the semiconductor memory device can sequentially successively read/write successive 3-address data by one access from the CPU.
Upon reception of start address information from the outside, the conventional semiconductor memory device sequentially successively accesses memory cells at three successive addresses in a memory cell array and reads out data from these memory cells in accordance with the start address information.
However, recent semiconductor memory devices increase in capacity and can store image data and CAD data in addition to general character codes. Accordingly, many memory cells are connected to one word line or bit line. To read/write data from/in these memory cells at a high speed, many memory cells must be precharged, or many sense amplifiers must always operate. Therefore, a large current flows through a power supply line to generate noise and increase the power consumption.
Upon completion of a read/write for one word line, an address corresponding to the next word line and the number of successive read/write data must be input again from the CPU. For this reason, in transferring a large amount of data, the CPU must frequently interrupt other processing operations and reset memories. This obstructs an increase in data processing speed.
From this viewpoint, a device is proposed in which a large-capacity memory cell array is divided into memory blocks, and data are read/written while respective areas in one divided memory block are successively accessed. Even in this semiconductor memory device, however, the CPU must reset an address and the like in order to read/write data from/in the next block. The CPU must temporarily interrupt other processing operations to access the memory. The processing load of the CPU increases, so the data processing speed of the CPU cannot satisfactorily increase.